Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Performance of a design instantiated in programmable logic and routing of an FPGA (“FPGA fabric”) may have delay or latency. However, such delay may vary with variations in semiconductor processing corners, power supply voltage, or operating temperature, or some combination thereof. These variables of process, voltage, and/or temperature are generally known as “PVT” variation. PVT variation may affect the timing relationship of a data link interface, including either or both a transmit side of a data link interface and a receive side of the data link interface.
As is known, configuration bits may be used to configure FPGA fabric routing and FPGA programmable logic fabric with FPGA fabric routing, where signal propagation delay is generally known within specified bounds. However, with respect to a SERDES application, a generally well-controlled data exchange interface is desirable, and delay variations due to PVT variation may cause phase noise. It should be understood that for a SERDES application, a transmit clock signal is a high speed clock signal for serial communication of data. Because of PVT variation, after an initial phase alignment between transmit and destination clock signals, a transmit clock signal often has to be readjusted in a conventional SERDES application, and such phase adjustments appear as phase noise or jitter.
While some SERDES applications generally have a fixed, namely varied within a small defined range, and controlled timing relationship for a data link interface, there may still be phase noise or jitter due to synchronizing to a received clock signal, whether provided as a separate clock signal or embedded within data. For purposes of clarity and not limitation, it shall be assumed that a clock is embedded in data, and thus recovered therefrom.
With respect to a receiver path having data and clock signaling following from an incoming data stream, output data from a physical-attachment layer clock domain thus may only get referenced to an embedded clock in such data stream but not any other stable reference clock. While the most closely aligned phase of a set of phases of a recovered clock may be aligned with respect to a physical-coding layer clock domain as an output clock to send data out of the physical-attachment layer clock domain, this initial alignment may be insufficient to support subsequent operation. In other words, such initial alignment may be insufficient due to changes caused by PVT variation and/or incoming data causing phase variations. By phase variations, it is generally meant the relationship between a selected phase of a recovered clock and a clock used in a physical-coding layer clock domain.
Accordingly, it would be desirable and useful to provide means to overcome one or more of the above identified limitations.